The invention relates generally to semiconductor structures and fabrication of semiconductor chips and, in particular, to methods of measuring thickness and dopant content of a layer of interest applied over a feature, particularly for layers of material including an atomic species distinct from that/those of the underlying layer(s), and more particularly for measuring dopant dosage in doped dielectric layers applied to devices and/or structures in the underlying layer(s), such as fins of finFETs, and apparatus therefor.
An integrated circuit (“IC”) is a device (e.g., a semiconductor device) or electronic system that includes many electronic components, such as transistors, resistors, diodes, etc. These components are often interconnected to form multiple circuit components, such as gates, cells, memory units, arithmetic units, controllers, decoders, etc. An IC includes multiple layers of wiring that interconnect its electronic and circuit components.
When features are coated with additional layers of material, it can become difficult to check them for suitable layer thickness and content. For example, one type of feature becoming more common in ICs is a so-called finFET—a field effect transistor with a vertical orientation that resembles a fin. Such finFETs can be formed in a number of ways and on a number of substrates, such as on silicon on insulator (SOI) wafers, bulk silicon (Si) wafers, and/or other substrates as may be appropriate and/or desired. When using SOI wafers that include a semiconductor substrate such as Si, a dielectric layer atop the semiconductor substrate often referred to as a BOX layer, and a layer of semiconductor atop the BOX layer, which can include monocrystalline silicon, known processes are used to form grooves in the silicon over the BOX layer to define the bases of fins and deposit dielectric over the whole article so that a layer of the dielectric material forms on the fin bases and other areas, such as a blanket pad region. Similarly, when using bulk Si substrate, known processes, such as etching, are used to form fins by forming grooves, the fins then being isolated using shallow trench isolation (STI), which includes depositing a dielectric material in trenches around the fins to isolate them. Some fabrication processes also dope a gate dielectric layer with a dopant, such as nitrogen (N), to enhance performance of the finFETs or otherwise alter their properties and/or behavior during operation. However, because of the topography of the finFETs, checking layer thickness and dopant concentration can be problematic.